Many electronic devices arc designed and developed with highly integrated hardware and software components. The electronic devices typically have multiple hardware components including one or more central processing units ("CPU"), static or dynamic memory such as Read Only Memory ("ROM) and Random Access Memory ("RAM"), memory management units, one or more caches, buses, timers, peripherals, and other components. Multiple software components such as device drivers, operating systems and application programs are used to interact with the multiple hardware components to provide a desired functionality.
As is known in the art, new electronic devices in the past were often designed around general purpose hardware components such as a general purpose central processing unit. Many times, a new electronic device was designed without having actual access to one or more general purpose hardware components. In such a scenario, the accessible hardware components of the electronic device were assembled (e.g., bus, memory and power supply) while other hardware components such as the central processing unit were replaced with an In-Circuit Emulator ("ICE") or other device that allowed the behavior of that hardware component to be emulated. Software components for the electronic device were then developed using the existing hardware components and the in-circuit emulator. When the new hardware component was available, it was inserted into the new electronic device and integrated with the developed software components.
As electronic device development became increasing complex, very few hardware components of the system were built without performing a design verification first. The design verification was used to confirm that hardware components result in a design that operates in accordance with predetermined functional specifications. Hardware Description Languages ("HDLs") were developed to emulate and verify the design of hardware components. Hardware description languages known in the art include Very High Speed Integrated Circuit Hardware Description Language ("VHSIC HDL" or "VHDL")), Programming Control Language ("PCL") and others. Hardware description languages provide a gate-level emulation of hardware devices. For more information on VHDL, see Institute of Electrical and Electronic Engineers ("IEEE") standard 1076, which is incorporated herein by reference. Hardware description languages generally include a set of instructions for sending and receiving data to an emulated device under test, storing and receiving data, and other interactions. This allows the behavior of a proposed hardware device to be verified before it is built.
In today's world, "co-verification" using simulation technologies allows developers to design and verify the behavior of hardware and software components in a new electronic device. Behavior of hardware and software components can be examined during a simulation by setting break-points, stopping the simulation at various states, and examining data generated by the simulation. Various simulations also allow certain hardware components to be emulated with a hardware description language while other hardware and software components are simulated.
Exemplary emulation/simulation environments using hardware description languages include: "Digital Circuit Design Assist System For Designing Hardware Units and Software Units in a Desired Digital Circuit, and Method Thereof," U.S. Pat. No. 5,493,507, by Shinde et al.; "Method and System for Creating, Deriving and Validating Structural Description of Electronic System From Higher Level, Behavior-Oriented Description, Including Interactive Schematic Design and Simulation," U.S. Pat. No. 5,544,067, by Rostoker et al; "Hardware Simulation and Design Verification System and Method," U.S. Pat. No. 5,600,579, by Steinmetz; and "Dynamic Software Model For Emulating Hardware," U.S. Pat. No. 5,715,433, by Raghavan, et al.
Hardware description languages provide a "hardware-centric" view of an electrical device. However, hardware description languages typically do not allow realistic simulation of timing or other interactions between hardware and software components. For example, hardware description languages may offer hardware emulation cycle rates of 10,000 cycles-per-second or less when an actual hardware component such as a central processing unit may actually execute at 200,000,000 or more cycles-per-second.
In addition, one of the most common and underestimated problems associated with the design of an electrical device is memory interaction. The speed and structure of memory typically has a significant impact on the performance of the electrical device. Existing emulators and simulators known in the art typically determine the internal behavior of memory every simulation or emulation cycle, and may further slow the execution of a simulation or emulation by an order of magnitude or more.
Thus, the slow speed of simulators and emulators using hardware description languages is unacceptable for determining many timing interactions between hardware and software components in a final system. As is known in the art, integration of hardware and software components in a final system is one of the most difficult problems encountered by developers of electrical devices.
There have been attempts to overcome some of the timing problems associated with simulators and emulators using hardware verification languages including: "Logic Simulation Using a Hardware Accelerator Together with an Automated Error Event Isolation and Trace Facility," U.S. Pat. No. 5,146,460, by Ackerman et al; "Timing Analysis for Logic Optimization Using Target Library Delay Value," U.S. Pat. No. 5,475,605, by Lin; and "Hardware-Software Debugger Using Simulation Speed Enhancing Techniques Including Skipping Unnecessary Bus Cycles, Avoiding Instruction Fetch Simulation, Eliminating the Need for Explicit Clock Pulse Generation and Caching Results of Instruction Decoding," U.S. Pat. No. 5,678,028, by Bershteyn, et al. However, as electronic devices continually increase in speed and require different types of high speed and low speed memory, such attempts to improve the timing problems still do not provide adequate simulation of timing interactions between hardware and software components in an electronic device.
In the last few years, electronics are not only executing at increased speeds but also significantly shrinking in size. These smaller, faster electronic devices include digital phones, pagers, wireless devices, hand held devices, personal digital assistants, and others. Many of these new faster smaller electronic devices use Application Specific Integrated Circuit chips ("ASIC"), Reduced Instruction Set Chips ("RISC") and other chips to provide a desired functionality in a small electronic device. For example, the M-Core processor by Motorola Corporation of Austin, Tex., and the Tri-Core processor by Siemens Corporation of New York, N.Y., provide low power chips with a reduced instruction set optimized to provide good code density and memory access efficiency for a small electronic device.
New electronic devices are also being implemented as a "System-on-a-Chip" ("SoC"). System-on-a-chip designs integrate processors, memory, buses, and other components selected by a designer on a single integrated circuit chip. An electronic device with a system-on-a-chip, is not designed with separate off-the-shelf hardware components due to space and power limitations. Instead, a system-on-a-chip is a custom chip specifically designed for a desired purpose in a specific electronic device. For example, the M-Core processor may be selected with high-speed RAM, a memory management unit, a bus, a serial port for sending and receiving text, and integrated in silicon or other materials on a single chip to create a system-on-a-chip (e.g., for a pager)
System-on-a-chip designs arc also making increased use of integrated hardware components to create complex embedded systems. For example, on-chip Digital Signal Processors ("DSP") are often used in connection with high-speed on-chip memory, pulling data from independent memory banks to improve processing bandwidth. A memory hierarchy with many different timing constraints may be used to reduce power consumption by storing commonly used data in on-chip instruction and data caches while less commonly used data and program overlays are stored in slower off-chip memory without caches. System-on-a-chip designs make it possible to customize the number and speed of on-chip components as well as off-chip peripherals and components for a proposed device with a pre-determined functionality.
However, system-on-a-chip designs present additional problems for simulators and emulators known in the art. As was discussed above, most simulators and emulators that use hardware design languages do not accurately reflect timing interactions among components of a system. This typically leads to complex problems during integration of hardware and software components, which is magnified for system-on-a-chip designs due to the potentially complex interaction of on-chip and off-chip components.
Many simulators and emulators that use hardware description languages also do not allow external or off-chip peripherals, memory, busses, Liquid Crystal Display controllers ("LCD") or other peripherals to be easily modeled for system-on-a-chip designs. Only internal or on-chip components are modeled. As a result, software developers are often forced to "stub" out routines that access off-chip peripherals, memories, buses, liquid crystal display controllers or other peripherals. This makes it difficult to develop device drivers for off-chip memory or peripherals and can also lead to complex integration problems such as bus and memory collisions. Thus, design flaws for off-chip components may be hidden until the system-on-a-chip is actually used with real off-chip hardware components.
New electronic devices often require multiple off-chip central processing units that cooperate and interact to exchange data. Many simulators and emulators that use hardware description languages known in the art do not allow multiple off-chip central processing units, that may have multiple on-chip and off-chip components themselves, to be easily modeled and do not allow data to be passed to/from such off-chip processing units to on-chip processing units. This limits the type of system-on-a-chip for a new electronic device that can designed and developed with existing simulators and emulators.
Thus, it is desirable to have a simulator or emulator that can be used to model on-chip and off-chip components as well as provide a more accurate representation of the interactions among on-chip and off-chip components including timing interactions for system-on-a-chip designs. The simulator should be capable of allowing system-on-a-chip as well as other electronic systems to be designed, verified and developed with a high level of confidence that the actual system will meet pre-determined design functionality for a new electronic device.